Among integrated circuit manufacturers there has developed a practice of forming a partially generic type of integrated circuit device, or chip, that can be subsequently made into a variety of different types of custom chips for various applications. These partially formed generic devices are sometimes referred to as a gate array type chip or a sea of gates. Typically, a gate array type chip is made up of numerous identical MOS or CMOS circuit elements. A specific custom chip, such as an Application Specific Integrated Circuit (i.e. ASIC), is then developed by electrically connecting the individual MOS or CMOS elements in some appropriate manner through conductive metal layers that are subsequently formed on the gate array chip. The specific patterns of the conductive layers thus determines the custom design aspects of the various integrated circuits, such as ASIC's, that are formed from the gate arrays. The individual MOS or CMOS elements of a gate array chip are generally uniformly spaced on portions of a surface of the chip. Typically, however, several MOS or CMOS elements in localized regions are functionally grouped together in what are termed cells, and electrically interconnected to form fundamental logic circuit elements, such as AND gates, OR gates and the like. More sophisticated circuit elements are then designed by interconnecting individual cells.
There is a natural desire among integrated circuit manufacturers to maximize the number of functions that can be performed by a single gate array type chip. Thus, the number of individual MOS or CMOS elements on a single gate array chip is normally fairly high, on the order of 600,000 to 1,000,000 individual elements. Typically, however, only half of all of these gates can be used in the subsequently made custom chip.
FIG. 1 shows a small set of identical MOS devices found on a conventional gate array type chip. Conventional production of prior art gate array type circuit structures typically involves the formation in a silicon wafer 2 of P-wells and N-wells to define areas or islands 10a-10d where one or more MOS or CMOS devices will be formed. Areas 10a-10d in FIG. 1 are thus P-islands and/or N-islands. A field oxide (not shown) is then grown on unmasked portions of the silicon wafer 2 to isolate each of the MOS islands 10a-10d from other devices on the wafer 2. After removal of the field oxide mask, a thin gate oxide layer is grown over portions of the islands 10a-10d, and a polysilicon layer is deposited over the gate oxide layer and other portions of the wafer 2. This polysilicon layer is subsequently patterned to form individual polysilicon strips 20 which form the gates in each of the MOS islands 10a-10d, along with contact pads or "dogbone" areas 28 that extend over the field oxide (not shown) surrounding the MOS islands 10a-10d. Source and drain regions 30 and 32 are then formed in the MOS islands 10a-10d by appropriate doping. A self-aligned silicide layer (not shown), sometimes termed a salicide, may also be formed over the polysilicon strips 20 as well as over the source and drain regions 30 and 32. Another layer of insulation, such as an oxide layer, is then formed over the entire structure and appropriate planerization may be performed.
At this stage in the fabrication of conventional gate array type chips, such as partially shown in FIG. 1, a generic structure has been formed with numerous essentially identical MOS devices such as the devices in MOS islands 10a and 10b disposed beneath the polysilicon strips 20. The particular devices are at this point electrically independent from other MOS devices formed beneath other polysilicon strips in other MOS islands or wells. Alternatively, MOS devices in adjacent islands, such as islands 10c and 10d, may be connected together by continuous polysilicon strips 20'a and 20'b. The island pairs 10c and 10d are still electrically isolated from other pairs in other islands, however, including the islands 10a and 10b shown in FIG. 1. Depending upon the desired electrical circuitry to the implemented in the partially fabricated gate array type chip, the various electrically isolated devices 10a, 10b and the like are then connected or "wired" together by formation of a metal layer over the previously deposited insulation layer (not shown) and patterning of this metal layer into a wiring harness made up of strips 40. Where more than one metal layer is to be used, a further insulation layer is deposited over the first metal layer (forming strips 40) before the additional metal layers are deposited and patterned. Thus separate insulation layers, typically oxide layers, separate each of the various metal layers.
Formation of electrical interconnections between the MOS gate electrodes, such as electrodes 20 of devices 10a and 10b also involves the formation of contacts 50 through the insulation layer (not shown) in order to provide a path from the metal strips 40 to the polysilicon pads 28. These contacts 50 are formed by making a hole in the insulating layer and filing this hole with a conductive material that provides an electrical path between the polysilicon contact pad 28 and the patterned metal layer 40. Similarly contacts 55 are also provided at various points to further provide contacts between the various source/drain regions 30 & 32 of each island 10a-10d and other metal strips residing in the same metal layer as the metal strips 40. Additionally, to appropriately bias the gate array substrate, various electrical connections must be normally made to miniature N and P wells or substrate taps 62 located on the substrate of the chip 2. These connections are typically provided by further metal strips (not shown) residing in the same patterned metal layer as the metal strips 40. Contacts 65 are made with the N and P substrate taps 62 by forming additional apertures through the intervening insulating layer between the patterned metal layer and the substrate, and again filling these apertures with a conductive material.
Due to the complexity of wiring necessary to develop various desired electronic circuit elements on a gate array type chip, it is often necessary to provide two and often even three patterned metal layers on a single array type chip in order to achieve all of the desired electrical interconnections and cross-over wirings between various active devices, such as those illustrated in FIG. 1. Since each contact opening or via formed between the polysilicon contact pads 28 and the overlying metal layer can result in electrical failure due to any one of misalignment, underetching, overetching, or improper filling of the via openings with conductive material, an increase in the number of via openings and patterned metal wiring layers of a gate array chip can have a negative impact on the overall yield of chips or dies developed from a semiconductor wafer. Additionally, the limited availability of space for necessary electrical interconnections, even among several metal layers, has been found to limit the total number of individual MOS or CMOS devices that can actually be employed on a single semiconductor chip. Accordingly, in some applications less than half of the individual MOS devices placed on a single gate array type chip may be actually used in the final custom designed chip due to the demands of cross-over wiring and cell interconnection.
It would be desirable if at least some of the electrical interconnections between various active devices on a substrate, such as the MOS devices in islands 10a-10d, bipolar and other types of active devices, could be carried out in a manner which would reduce the number of contacts needed between the gates or other conductive material portions of the individual devices and the various metal layers. It would similarly be desirable to eliminate the need for at least one of the numerous metal wiring layers typically needed to form a complete wiring harness for the gate array chips, while still permitting the initial formation of a partially generic gate array type structure that is capable of being subsequently electrically connected together to form a variety of different electrical circuits.
Integrated circuit manufacturers also continue to expend considerable resources attempting to implement complex logic circuitry on smaller areas of the semiconductor substrate of the gate array chips and to increase the density and functionality of the MOS devices populating the substrate. While it would be desirable to reduce the size of each of the individual MOS devices, it has also been determined that process limitations and detrimental parasitic effects in the MOS devices themselves limit the degree to which, for example, the length of the gate elements of the individual MOS devices can be reduced.
Accordingly, the number of MOS type devices that can be effectively used in gate array type chips depends on a number of limiting factors, including the size of the individual MOS devices, the number of interconnections between the MOS devices forming a local functional cell, and the number of interconnections between various cells making up the gate array chip. Nonetheless, there still exists in the circuit manufacturing community a keenly felt need to continue increasing the number of individual MOS devices that may be formed on a gate array chip and effectively utilized when the partially generic gate array chip is processed to form a custom design. The present invention fulfills this need.